SoC Physical Verification Lead – Tapeout Signoff

Deel is seeking an experienced SoC Physical Verification Engineer in the United Kingdom to lead full-chip and hierarchical signoff, including DRC, LVS, ERC, PERC, and DFM. You will work with PD, CAD, RTL, and EDA vendors to ensure tapeout-ready silicon and robust reliability across next-generation designs.

The role requires hands-on leadership, strong debugging, and scripting skills, with experience in advanced nodes and memory-centric SoCs.

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