Overview
In this role you will drive power efficiency and performance for Arm’s compute solutions, shaping UPF-based power intent across multi-domain SoCs. You’ll collaborate with cross-functional teams to define power architectures, validate UPF files, and influence PDN tradeoffs to deliver high-quality results for partners. The position offers exposure to cutting-edge EDA flows and opportunities to impact future chip design at scale. You will work in a collaborative, innovative environment that values practical problem-solving and clear communication.
Pay / Benefits
- Competitive compensation package
- Benefits
- Career growth and professional development opportunities
- Hybrid working options
- Collaborative and innovative environment
Responsibilities
- Define and implement power intent specifications for SoC designs with cross-functional teams
- Produce, maintain, validate UPF files describing power domains, states, retention, level shifters, and isolation
- Merge UPF across hierarchical domains and ensure accuracy across PDN considerations
- Investigate PDN tradeoffs and power distribution to optimize power intent
- Enable partners to achieve high-quality results through robust power intent definitions
Key requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field
- Solid understanding of power intent concepts (voltage islands, power domains, power states, power control architectures)
- Proficiency in UPF 2.0/2.1/3.0/3.1 and experience in low power formal verification
- Excellent communication and collaboration skills
- Proven track record with power intent definition and verification
- The ability to express insights clearly and communicate them effectively
- Excellent communication and collaboration skills
- Teamwork and customer focus
- Creativity and innovation
- UPF 2.0/2.1/3.0/3.1 (Unified Power Format)
- Low power formal verification
- Formal verification tools (Conformal LP)
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