Senior SoC Physical Verification Lead – Tapeout Signoff

Aion Silicon Ltd. seeks an experienced SoC Physical Verification Engineer to lead signoff for next generation logic and memory-centric designs.

You will ensure tapeout-ready silicon by performing DRC, LVS, ERC, PERC, DFM, and reliability checks, driving methodology and signoff with PD, CAD, RTL, and foundry teams. You will develop automation, AI-assisted workflows, and regression infrastructure while collaborating with EDA vendors and fabs, including direct TSMC interaction from kickoff to

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