Sr. Systems Validation Engineer (SerDes)

Overview

In this role you will validate high-speed SerDes PHYs and drive robust validation across PVT conditions for next-gen satellite communication hardware. You will collaborate with cross-functional teams to shape test plans, automate verification, and contribute to product quality for advanced ASICs and silicon products. You will work with cutting-edge lab equipment to understand eye diagrams, jitter, and stressed-eye performance, delivering actionable insights. This is a fast-paced, engineering-focused opportunity with a meaningful impact on satellite communication capabilities.

Responsibilities

• Validate high-speed SerDes PHYs and perform link bring-up, equalisation and performance testing
• Execute chip and system validation across Process, Voltage and Temperature (PVT) conditions
• Utilise lab equipment (oscilloscopes, BERT, DCA, PNAX) for eye diagram, jitter and stressed-eye testing
• Develop and execute chip and system test plans in collaboration with engineering teams
• Create automated test solutions using Python and investigate root causes of validation issues
• Analyse test data, support CI and contribute to product quality improvements

Key requirements

• Bachelor’s or Master’s degree in Electronic Engineering, Computer Engineering or related discipline
• 8–13 years’ post-graduate experience in chip or system validation
• Experience testing telecommunications or satellite systems (analog, RF, high-speed blocks)
• Strong knowledge of SerDes technology, RF fundamentals and communications theory
• Proficiency in Python, C/C++ or similar for test automation
• Experience with RF test equipment, debugging, and tools such as JIRA and Confluence
• Excellent problem-solving, communication and teamwork skills in fast-paced environments

• problem-solving
• communication
• teamwork
• SerDes technology
• RF fundamentals
• Python

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