Field-Programmable Gate Arrays Engineer

Job Overview

I’m getting in touch because I’m supporting a client who are pushing the boundaries of high‑performance IP on next generation FPGA and Adaptive SoC platforms and your experience looks highly relevant. The role is fully remote from the UK with genuine technical ownership and a culture that respects engineering excellence. If this aligns even just slightly with what you’d consider for your next move, would you be open to a brief conversation?

Technical Requirements

• Strong SystemVerilog RTL capability
• Confident across 100Gb Ethernet, PCIe Gen5, and AXI
• Comfortable taking designs through to timing closure without fuss
• Experience with Vivado and Vitis
• Proficient in Python or TCL to streamline work
• Familiar with modern development practices, Git, and CI

Employment Details

• Seniority level: Mid‑Senior level
• Employment type: Contract
• Job function: Information Technology, Consulting, and Engineering
• Industries: Staffing and Recruiting, Robotics Engineering, and Engineering Services

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