Yoh, A Day & Zimmermann Company in Southampton is seeking a hands-on Senior FPGA Design Engineer to develop RTL and integrate IP blocks for FPGA and ASIC. The role covers the full development flow, from writing Verilog/SystemVerilog to timing closure, synthesis and lab validation.
You will collaborate across teams, focusing on real-time, high-speed FPGA design with signal processing knowledge as a bonus and familiarity with AMBA protocols. This is a hybrid role with two days onsite per week.
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