Ultra-Low Latency C++ Engineer with FPGA Trading

Company: Testing Site – JPMC
Apply for the Ultra-Low Latency C++ Engineer with FPGA Trading
Location: London
Job Description:

JPMorganChase in London seeks an Ultra Low Latency C++ Lead Software Engineer within the Electronic Trading Technology team to design, build, and operate market gateway solutions with FPGA acceleration. You will collaborate with hardware and software teams to achieve deterministic performance and high reliability in production trading systems.

Responsibilities include leading latency optimization, developing across Unix/Linux, and ensuring observability and resiliency.

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Posted: October 21st, 2026