Digital Electronics Principal Verification Engineer

Overview

As a Digital Electronics Principal Verification Engineer, you will help drive verification strategy for Cadence’s Chiplet-enabled IP. You will work with a cross-functional team to build scalable verification and emulation environments, enabling rapid, reliable SoC development. You will define metrics, build UVM-based scoreboards, and implement formal and emulation-based verification flows. This role places you at the forefront of Cadence IP solutions, shaping how customers accelerate time-to-volume. You will collaborate with architects and designers to tackle complex test scenarios and improve verification effectiveness.

Responsibilities

• Develop verification and emulation environments for complex chiplet designs
• Create UVM-SV scoreboards for self-checking regressions
• Define functional coverage within metric-driven verification environments
• Develop SystemVerilog Assertions for formal and simulation use
• Build emulation environments using Cadence Palladium
• Integrate Cadence verification IP for simulation and AVIP for emulation
• Define and manage verification plans using vManager
• Create automated regression environments (e.g., Jenkins, GIT)
• Participate in ISO-9001 review processes and cross-functional technical meetings
• Collaborate with architects and design engineers to debug complex test scenarios

Key requirements

• Degree in Electrical/Electronic Engineering, Microelectronics, or related
• 10+ years in microelectronics/EDA
• Experience of Verilog RTL Design
• Experience of Metric Driven Verification (MDV)
• Experience of Formal Verification Methodologies
• Excellent oral and written English
• Self-motivated with strong planning and communication skills

• excellent communication
• interpersonal skills
• team collaboration
• Verilog RTL Design
• Metric Driven Verification (MDV)
• Formal Verification Methodologies

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