Design Verification Engineer

Overview

In this Verification Engineer role, you join a leading SoC team focused on cutting-edge 5nm designs, high-speed interfaces, and NAND storage solutions. You will contribute across the full development lifecycle in a fast-moving, startup-like UK arm backed by a global company. You will tackle complex design challenges in multi-CPU architectures and accelerators, shaping verification environments and methodologies. This is an opportunity to impact high-performance storage technology while working with cross-functional teams.

Pay / Benefits

• Competitive base salary
• Hybrid working model
• Generous company pension scheme
• Private health insurance
• Visa sponsorship and relocation support for experienced engineers

Responsibilities

• SoC architecture collaboration and RTL design input
• verification planning and execution across blocks
• defining functional requirements for verification environments and metrics
• developing SystemVerilog UVM testbenches
• constraint-driven verification and validation
• synthesis and FPGA prototyping
• post-silicon support and debug
• collaboration across multi-disciplinary teams to meet design goals

Key requirements

• Bachelor’s or Master’s degree in Electronic Engineering (or related field)
• Experience in digital ASIC design and verification
• Defining functional requirements for verification environments & metrics
• SystemVerilog UVM testbenches
• Formal proof verification
• Understanding of C test cases and C code
• Scripting languages (e.g. Python, Perl, TCL)

• SystemVerilog UVM testbenches
• Formal proof verification
• Understanding of C test cases and C code
• Scripting languages (Python, Perl, TCL)
• Formal verification tools (JasperGold, VC Formal)
• C/C++ development

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