Digital ASIC Design Engineer

Company: Intellectual Capital Resources
Apply for the Digital ASIC Design Engineer
Location: Bristol
Job Description:

Overview

As a Digital ASIC Design Engineer, you will own and optimize complex hardware modules for cutting-edge graphics processors. You’ll work with cross-functional teams to advance silicon solutions and influence architectural decisions. The role focuses on delivering high performance, low power, and reliable designs for next-generation GPUs. You will mentor junior engineers and contribute to ongoing innovation in GPU silicon technology. This is an opportunity to impact product architecture and development at scale.

Pay / Benefits

  • competitive base salary
  • bonus scheme

Responsibilities

  • Collaborate with design, verification, and validation teams to deliver silicon solutions
  • Define and document micro-architecture specifications and execution plans
  • Analyse and optimise designs for performance, area, and power trade-offs
  • Participate in design reviews and provide constructive technical feedback
  • Maintain and improve the design environment, debug and resolve design issues
  • Plan, schedule, and deliver work packages within timelines
  • Stay current with emerging tools, methodologies and best practices in silicon design
  • Mentor graduate engineers and early-career colleagues

Key requirements

  • Strong knowledge of digital IC design techniques and methodologies
  • Hands-on experience with RTL design at IP or SoC level using SystemVerilog
  • Proven ability to optimise designs across performance, power, and area
  • Experience with ASIC or FPGA design tools and environments
  • Exposure to formal verification or proof methodologies to validate design intent
  • Knowledge of CPU, DSP, or FPU architectures, including debug and test strategies
  • Proficiency in C, SystemC, C++, Python, Perl, or TCL
  • Understanding of verification requirements from specifications
  • Experience with GPU or CPU design methodologies, including UVM
  • Collaborative teamwork
  • Clear, constructive feedback during design reviews
  • Mentorship and capability development of junior engineers
  • SystemVerilog RTL design
  • ASIC/FPGA design tools
  • Formal verification / proof methodologies

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Posted: October 17th, 2026