ASIC Design Engineer

Overview

In this Senior ASIC Design Engineer role, you will contribute to the development of complex ASICs across the full silicon lifecycle. You will work in a collaborative engineering team with ownership of projects and cross-project impact. The role combines hands-on design with architectural understanding, enabling you to influence multiple stages from specification to silicon delivery. You will join during a growth phase, partnering with a leading technology company to push cutting-edge ASIC solutions.

Responsibilities

• Own and drive the design of complex ASICs across the full silicon development lifecycle
• Contribute across multiple aspects of ASIC development within a collaborative team
• Take ownership of projects and deliver with autonomy
• Apply RTL design and verification expertise to deliver high-quality silicon
• Collaborate with cross-functional teams and partner organisations to meet programme goals

Key requirements

• RTL design experience using VHDL or Verilog
• Experience with SystemVerilog
• Experience leading or owning ASIC design projects
• Knowledge of UVM verification methodologies
• Experience using industry-standard EDA tools
• Good understanding of SoC architectures, CPU architecture, and DSP

• collaboration
• ownership
• communication
• VHDL
• Verilog
• SystemVerilog

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