ESD Engineer

Overview

In this ESD Engineer role, you will drive the I/O library development, leading design, simulation, and validation of advanced ESD and latch-up protected I/O structures. You’ll shape chip- and IP-level ESD methodologies and ensure robustness across Cirrus Logic’s mixed-signal portfolio. Collaboration with foundry partners and internal teams will be key to updating libraries and rules. This high-impact position offers the chance to influence product reliability and contribute to a culture of innovation and excellence.

Responsibilities

• Design, simulate, and optimize advanced I/O circuits and ESD protection structures
• Characterize and model I/O libraries to support high-performance mixed-signal design flows
• Release, maintain, and improve I/O libraries and models used across multiple design teams
• Apply deep expertise in ESD and latch-up requirements to ensure robust, reliable silicon
• Drive ESD sign-off for chip-level and block-level designs, ensuring consistent methodology
• Act as a technical leader, unifying ESD, latch-up, and I/O strategies across business units

Key requirements

• MSc in Electrical Engineering (or equivalent experience)
• Holistic understanding of ESD/EOS protection for mixed-signal CMOS circuits
• Strong fundamentals in ESD circuit design, layout, and testing
• Proven experience in I/O design, including CMOS circuitry, latch-up mitigation, physical verification, and device-level characterization
• Chip-level ESD signoff expertise and understanding of reliability requirements
• Ability to guide layout engineers for robust ESD-safe layouts
• Proficiency with Cadence schematic capture, layout, and simulation tools
• Ability to work independently and lead/collaborate within high-performing technical teams
• Clear, effective written and verbal communication
• Experience in IBIS model generation is a plus

• Clear, effective communication
• Team leadership and collaboration
• Ability to work independently and lead projects
• Cadence schematic capture, layout, and simulation tools
• ESD circuit design, layout, and testing
• Latch-up mitigation

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